Method for storing data in a memory device with the possibility of access to redundant memory cells

专利摘要:
The present invention relates to a data storage method of a memory device having accessibility to redundant memory cells. A data storage method of a memory device having a memory cell arranged in memory cell columns and memory cell columns, and generating a system defect that occurs when a defective memory cell is removed, wherein the memory device has a redundant memory memory. Providing cells; Providing a preset access mode to access the redundant memory cells; And replacing a defective memory cell with the surplus memory cells by a predetermined access mode during operation of the memory device.
公开号:KR20030066435A
申请号:KR10-2003-0006674
申请日:2003-02-04
公开日:2003-08-09
发明作者:베네딕스알렉산더；단코우스키스테판；두에르거라인하드；러프볼프강
申请人:인피니온 테크놀로지스 아게；
IPC主号:

专利说明:

Method for storing data in a memory device with the possibility of access to redundant memory cells}
[12] The present invention relates to a data storage method and a data storage device, and more particularly, to a memory device having memory cells arranged in memory cell columns and memory cell columns, wherein the defective memory cell is removed and generates a system defect. A method of storing data.
[13] During the design, design and configuration of the memory module, it is inevitable that a system error caused by a defective memory cell will occur during the operating time of the memory module, i.e. when the memory module is in a running state on the circuit.
[14] The exact syntactic phrase of the memory module is meaningless, hereinafter, the memory module is mainly referred to as a "memory device".
[15] As the complexity of electronic circuits increases and the high integration of circuit units ("chips") increases day by day, system errors caused by electromigration or the like are problematic for the reliability of memory modules.
[16] Many electronic systems in which memory units are arranged are very sensitive to the occurrence of memory cell defects, so the requirements including the availability and reliability of memory units are increasing with high integration.
[17] Due to the increased complexity of electronic circuits, there is a need to balance the efficiency of circuit design with the idea of the hardware to be developed.
[18] Existing hardware ideas require that they be usable in other circuit environments, even when defective memory cells are generated.
[19] FIG. 2 shows a diagram of time when a memory cell defect occurred in a conventional memory device, showing a conventional sequence.
[20] In FIG. 2, reference symbol 201 indicates conventional system availability, which may vary between 0% and 100%.
[21] The time axis (" time ") 202 indicates time at different points and is arranged on a scale capable of indicating the progress of time from the occurrence of the memory cell defect 203 to the end of the boot operation 207.
[22] Conventionally, the entire system has been switched off at the time when the memory cell defect 203 occurs, so that the onset of system error 204 occurs shortly after the memory cell defect 203 occurs.
[23] As a result of conventional system failures, system availability 201 drops from 100% (estimated that no other fault will occur) to 0%.
[24] Eventually, the faulty hardware is replaced at the expense of time and waste in the case of complex electronic systems. The reference symbol 206 is designated as a so-called memory exchange period.
[25] After the memory exchange period 206, the entire system error is terminated, that is, the conventional system availability 201 progresses from 0% and slowly increases again.
[26] After boot time period 208, conventional full (100%) system availability 201 is reached again at the end 207 of the boot operation.
[27] As a result, a disadvantage of the conventional method for removing memory defects is the long system error time generated by the sum of the memory swap period 206 and the boot time period 208, as shown in FIG.
[28] In addition, a disadvantage of the conventional method for restoring system availability 201 is that under certain environmental conditions to avoid overall system failure, replacing defective hardware or switching off the entire system is expensive and impractical. have.
[29] Accordingly, it is an object of the present invention to allow redundant memory cells to be accessed in a manner that avoids restarting or booting the system.
[30] This object according to the present invention is achieved by the method described in claim 1 and the memory device having the features of claim 9.
[31] Further details of the invention are included in the dependent claims.
[1] FIG. 1 shows a timing chart that allows defective memory cells of a memory device to be replaced by surplus memory cells of the memory device during operation of the memory device.
[2] 2 shows a timing chart of a conventional method for replacing defective memory cells.
[3] <Explanation of symbols for the main parts of the drawings>
[4] 1: Generation of defects in the memory cell 2: Defect location measurement and excess selection bypass
[5] 3: surplus memory cell access 4: reestablish overall system availability
[6] 101: system availability 102: reduced system availability
[7] 103: time axis 201: conventional system availability
[8] 202: time axis 203: memory cell defect occurred
[9] 204: Start system error 205: End system error
[10] 206: memory replacement time period 207: start end cycle
[11] 208: boot time cycle
[32] The essential concept of the present invention is to ensure that when a memory cell fails, system availability is maintained completely or at least partially, that is, redundant memory cells appear in the memory device in lieu of the function of the defective memory cell. have.
[33] Thus, one of the advantages of the present invention is that system availability (which is likely to be slightly reduced) can be maintained even in the event of a memory cell failure.
[34] In addition, the method of the present invention is that the remaining surplus memory cells can be effectively used at all times, thereby enabling the development of economical circuits.
[35] In particular, there is no need to replace system components in the event of a system failure caused by a defective memory cell.
[36] In this way, no additional hardware costs are incurred, and a cost effective procedure for memory cell defects is achieved.
[37] Moreover, an advantage of the method according to the invention is that the time of reduced system availability is reduced, so that replacement of defective memory cells can be performed in a short time during operation of the memory unit.
[38] The present method for storing data in a memory device having memory cells arranged in memory cell columns and memory cell columns and having a system defect that occurs while a defective memory cell is being removed comprises the following steps.
[39] a) providing redundant memory memory cells to the memory device;
[40] b) providing a preset access mode for accessing the redundant memory cells
[41] c) replacing a defective memory cell with the excess memory cells by a predetermined access mode during operation of the memory device.
[42] Improvements to each of the problems to be achieved, and thus the advantages of the present invention can be found in the dependent claims.
[43] According to one preferred aspect of the present invention, the replacement of a defective memory cell with a redundant memory cell can be defined in a recoverable manner. A surplus memory cell that is already allocated to replace a defective memory cell may be provided to another memory cell having a defective memory device.
[44] According to another refinement of the present invention, a preset number of redundant memory cell columns or a preset number of redundant memory cell columns is provided.
[45] Thus, if possible, as an advantageous method, the system is intended for the replacement of defective memory cells or defective memory cells in which the corresponding memory cell column or corresponding memory cell column is defective in the event that a defective memory cell occurs in the memory device. You can determine if it is used.
[46] As another advantageous method, the replacement is accomplished by simultaneously programming the register containing the activation bit and the defective column or the column address.
[47] According to another refinement of the invention, the replacement of defective memory cells of the memory device is based on the replacement of at least one memory cell column and / or at least one memory cell column based on a preset access mode during operation of the memory device. It is done by
[48] According to another refinement of the invention, the replacement of defective memory cells in the memory device may be achieved by programming the access register with the start bit and at least one address of the memory cell column and / or the memory cell column being alternatively provided, The operation is performed based on a preset access mode during operation of the memory device.
[49] According to another refinement of the invention, a preset access mode for accessing redundant memory cells during operation of the memory device is provided by the test mode of the memory device.
[50] According to another refinement of the invention, redundant memory cells are provided for storing additional information items describing the correction of defects.
[51] As a result, it is possible to record information on the occurrence of defective memory cells.
[52] A memory device according to the present invention is:
[53] a) memory cells arranged in memory cell columns and memory cell columns and used to store data; and
[54] b) redundant memory cells for replacing defective memory cells during operation of the memory device.
[55] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[56] Like reference numerals in the drawings indicate identical or functionally identical components or steps.
[57] The timing chart shown in FIG. 1 shows that system availability 101 does not drop completely to 0% during the entire operation of the system or memory device in which the memory device is integrated, or during the entire operation time.
[58] A profile 103 of system availability is printed about the time base (" time ") 103, which assumes that a memory cell defect occurred during the operating time of the memory device.
[59] Initially, it is assumed that 100% system availability 101 appeared initially.
[60] If a memory cell defect, indicated at 1 in FIG. 1, occurs, system availability will be reduced. This is assumed to be caused by a memory cell defect reduced to a value at which the system availability is reduced, in other words reduced system availability 102 (indicated by the dashed line in FIG. 1).
[61] Even if system availability 101 appears to be reduced (only finely), the operation of the memory device is made.
[62] After a defect of the memory cell has been generated (step 1), positioning and redundancy selection for the defect are made in step 2 (see Fig. 1).
[63] When a defective memory cell is generated, the system determines whether the corresponding memory cell columns or memory cell column are replaced.
[64] The replacement is accomplished by programming a register with the start bit and the address of the column or column with the fault.
[65] In such a case, an access register is needed for each excess memory cell row or memory cell column.
[66] Position measurement of defective memory cells and selection or access to redundant memory cells is accomplished as shown in FIG. 2.
[67] If location measurement and redundancy selection for a fault are performed in step 2, the system provides a bypass to access the redundant memory cells in the access register.
[68] The access register provides a bypass in step 3, followed by step 2, to prevent a reduction in system availability 101.
[69] As a result, bypass for fault location, redundant selection and bypass for accessing redundant memory cells can be provided during the operating time of the memory device.
[70] After the progress of step 3, the defective memory cells are replaced with redundant memory cells, so that the system continues to step 4 where the pool (100%) system availability 101 is restored.
[71] Moreover, the system is provided for storing additional information items that describe the correction of defects in the memory device.
[72] Recognition of the memory cell, which stores additional information items describing defect correction, facilitates the determination of defect progression within the memory device and allows for quick finding of memory cell defects.
[73] As shown in Fig. 2, the time progression of the conventional method for replacing defective memory cells in a memory device is described in the introduction.
[74] While the invention has been described as preferred and exemplary embodiments, it is to be understood that the invention is not limited to these embodiments and can be modified in various ways. In addition, the present invention is not limited to the above-described applicability.
[75] As described above, the present invention has the advantage that, when a memory cell fails, the system availability is maintained completely or at least partially, that is, the redundant memory cell takes over the function of the defective memory cell. .
[76] Therefore, system availability can be maintained even in the event of a fault in a memory cell.
[77] The method of the present invention is that the remaining surplus memory cells can be effectively used at all times, thereby enabling the development of economical circuits.
[78] In particular, in the event of a system failure caused by a defective memory cell, no system components need to be replaced, no additional hardware costs are incurred, and a cost effective procedure for memory cell defects is achieved.
[79] An advantage of the method according to the invention is that the time of reduced system availability is reduced so that replacement of defective memory cells can be performed in a short time during operation of the memory unit.

权利要求:
Claims (10)
[1" claim-type="Currently amended] A method for storing data in a memory device having memory cells arranged in memory cell columns and memory cell columns and having a system defect that occurs when a defective memory cell is removed, the method comprising:
a) providing redundant memory memory cells to the memory device;
b) providing a preset access mode for accessing the redundant memory cells
c) replacing the defective memory cell with the redundant memory cells by a preset access mode during operation of the memory device. How data is stored.
[2" claim-type="Currently amended] 2. The data storage of a memory device having accessibility to the redundant memory cell according to claim 1, wherein the replacement of the defective memory cell with the redundant memory cell is provided in a reversible fashion. Way.
[3" claim-type="Currently amended] The method of claim 1 or 2, wherein the redundant memory cells are provided in a predetermined number.
[4" claim-type="Currently amended] 4. A method according to any one of claims 1 to 3, wherein the surplus memory cells are provided in a predetermined number.
[5" claim-type="Currently amended] The method of claim 3 or 4, wherein the replacement of the defective memory cells of the memory device is based on at least one memory cell column and / or at least one memory cell column based on a preset access mode during operation of the memory device. A data storage method of a memory device having accessibility to a surplus memory cell, characterized by the replacement.
[6" claim-type="Currently amended] 6. The method of claim 1, wherein the replacement of the defective memory cells of the memory device comprises the programming of an access register with alternately provided start bits and at least one address of a memory cell column and / or a memory cell column. Thereby performing access based on a predetermined access mode during operation of the memory device.
[7" claim-type="Currently amended] 6. A method according to any of claims 1 to 5, wherein a preset access mode for accessing redundant memory cells during operation of said memory device is provided by a test mode of the memory device. How to store data on a memory device.
[8" claim-type="Currently amended] 2. The method of claim 1, wherein redundant memory cells are provided for storing additional information items describing the defect correction.
[9" claim-type="Currently amended] a) memory cells arranged in memory cell columns and memory cell columns and used to store data; and
b) data storage device of a memory device having accessibility to a redundant memory cell comprising redundant memory cells for replacing defective memory cells during operation of the memory device.
[10" claim-type="Currently amended] 10. The data storage device of claim 9, wherein redundant memory cells are provided for storing additional information items describing defect correction.

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同族专利:

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公开号 | 公开日

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TW200303027A|2003-08-16|

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KR100520838B1|2005-10-12|

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US20030160288A1|2003-08-28|

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DE10204409A1|2003-08-14|

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DE10204409B4|2008-04-24|

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TWI287799B|2007-10-01|

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US6819606B2|2004-11-16|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2002-02-04|Priority to DE2002104409

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2002-02-04|Priority to DE10204409.0-53

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2003-02-04|Application filed by 인피니온 테크놀로지스 아게

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2003-08-09|Publication of KR20030066435A

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2005-10-12|Application granted

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2005-10-12|Publication of KR100520838B1

优先权:

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申请号 | 申请日 | 专利标题

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DE2002104409|DE10204409B4|2002-02-04|2002-02-04|Method for storing data in a memory device with access to redundant memory cells|

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DE10204409.0-53|2002-02-04|